Structural abstractions in the .pin file that segment the DUT into independent functional groups.
Maintaining high yield requires strict adherence to system calibration standards.
Chain the tests together inside the Test Flow editor to dictate how the device moves from one test block to the next. 5. Coding Custom Test Methods (C++ API Examples) verigy 93k tester manual
) through the PPMU to bias protection diodes. It measures the resulting voltage drop to confirm a solid electrical connection. Gross Leakage ( IIHcap I sub cap I cap H end-sub IILcap I sub cap I cap L end-sub
The Verigy 93000 uses a smart, modular design. This means you can change its parts to test different kinds of chips. Tester Processor and Workstation Structural abstractions in the
The you are running (e.g., SmarTest 7 or SmarTest 8)
The represents a cornerstone of modern semiconductor testing. Known for its scalability, flexibility, and "test processor per pin" architecture, the V93000 platform—now managed by Advantest —has dominated the System-on-Chip (SoC) and System-in-Package (SiP) test markets for over a decade. Gross Leakage ( IIHcap I sub cap I
Window or edge placements for sampling DUT output data. Vectors / Digital Patterns (.mpat / .binl)
Defines clock periods, edge placements, drive windows, and compare windows.
The hardware is controlled and programmed through a sophisticated software suite. The official documentation—the "verigy 93k tester manual"—is intricately tied to this software.